Methods Of Manufacturing High Electron Mobility Transistors

ABSTRACT

The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2010-0097417, filed on Oct. 6, 2010, in the KoreanIntellectual Property Office (KIPO), the entire contents of which isincorporated herein by reference.

BACKGROUND

1. Field

Example embodiments relate to methods of manufacturing semiconductordevices.

2. Description of the Related Art

High electron mobility transistor (HEMTs) include semiconductors withdifferent band gaps and/or polarizabilities. The semiconductors arecombined to form a heterojunction. A first semiconductor with a largeband gap and/or large polarizability operates as a donor. A2-dimensional electron gas (2DEG) is induced in a second semiconductorwith a smaller band gap and/or polarizability by the firstsemiconductor, at the heterojunction between the first and secondsemiconductors. The 2DEG may be used as a channel in the HEMT.

A HEMT may be used as an increased electron mobility semiconductordevice and/or as a power transistor. A HEMT may include a semiconductorwith a wide band gap, for example a compound semiconductor. Accordingly,a breakdown voltage of the HEMT may be high.

SUMMARY

Example embodiments may provide methods of manufacturing metal-oxidesemiconductor field effect transistor (MOSFET) type normally-off highelectron mobility transistors (HEMTs) with high and/or improved outputusing impurity injection.

According to example embodiments, a method of manufacturing a highelectron mobility transistor (HEMT) includes forming a first materiallayer on a substrate, increasing electric resistance of the firstmaterial layer, forming a source pattern and a drain pattern, which arespaced apart from each other, on the first material layer havingincreased electric resistance, forming a gate insulation layer on thefirst material layer, between the source pattern and the drain pattern,and forming a gate electrode, a source electrode, and a drain electroderespectively on the gate insulation layer, the source pattern, and thedrain pattern. The source pattern and the drain pattern are formed of amaterial having a higher band gap than the first material layer.

The increasing of the electric resistance of the first material layermay include injecting impurities in the first material layer. Theforming of the source pattern and the drain pattern may include forminga second material layer having a higher band gap than the first materiallayer, on the first material layer having the increased electricresistance and forming the source and drain patterns by patterning thesecond material layer. The forming of the source pattern and the drainpattern may include forming a growth blocking layer defining an areawhere the source and drain patterns are to be formed on the firstmaterial layer having the increased electric resistance, and covering anarea where the gate electrode is to be formed, forming the source anddrain patterns in the defined area of the first material layer havingthe increased electric resistance and removing the growth blockinglayer.

The growth blocking layer may have a thickness for blocking injection ofthe impurities. The growth blocking layer may have a thickness forpenetrating through the impurities. A thickness of the growth blockinglayer for defining the area where the source and drain patterns are tobe formed, and a thickness of the growth blocking layer for covering thearea where the gate electrode is to be formed may be different from eachother. If the growth blocking layer has a thickness that blocksinjection of impurities, the method may further include, after removingthe growth blocking layer, injecting impurities into an area where thegrowth blocking layer for defining the area where the source and drainpatterns are to be formed is removed.

According to further example embodiments, a method of manufacturing ahigh electron mobility transistor (HEMT) includes forming a first layerincluding a first material on a substrate, increasing an electricalresistance of at least a part of the first layer, forming a sourcepattern and a drain pattern spaced apart from each other on the firstlayer, the source and drain patterns including a third material, a bandgap of the third material greater than a band gap of the first material,forming a gate insulation layer on the first layer between the sourcepattern and the drain pattern, forming a gate electrode on the gateinsulation layer, forming a source electrode on the source pattern, andforming a drain electrode on the drain pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingbrief description taken in conjunction with the accompanying drawings.FIGS. 1-20 represent non-limiting, example embodiments as describedherein.

FIGS. 1-6 are cross-sectional diagrams illustrating methods ofmanufacturing high electron mobility transistors (HEMTs) according toexample embodiments;

FIGS. 7-11 are cross-sectional diagrams illustrating methods ofmanufacturing HEMTs according to other example embodiments;

FIGS. 12-17 are cross-sectional diagrams illustrating methods ofmanufacturing HEMTs according to still other example embodiments; and

FIGS. 18-20 are cross-sectional diagrams illustrating methods ofmanufacturing HEMTs according to yet other example embodiments.

It should be noted that these figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feature.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference tothe accompanying drawings, in which example embodiments are shown.Example embodiments may, however, be embodied in many different formsand should not be construed as being limited to the embodiments setforth herein; rather, these embodiments are provided so that thisdisclosure will be thorough and complete, and will fully convey theconcept of example embodiments to those of ordinary skill in the art. Inthe drawings, the thicknesses of layers and regions are exaggerated forclarity. Like reference numerals in the drawings denote like elements,and thus their description will be omitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers indicate like elementsthroughout. As used herein the term “and/or” includes any and allcombinations of one or more of the associated listed items. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon”).

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of exampleembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, example embodiments should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle may have rounded or curved features and/or a gradient ofimplant concentration at its edges rather than a binary change fromimplanted to non-implanted region. Likewise, a buried region formed byimplantation may result in some implantation in the region between theburied region and the surface through which the implantation takesplace. Thus, the regions illustrated in the figures are schematic innature and their shapes are not intended to illustrate the actual shapeof a region of a device and are not intended to limit the scope ofexample embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

FIGS. 1-6 are cross-sectional diagrams illustrating methods ofmanufacturing high electron mobility transistors (HEMTs) according toexample embodiments. Referring to FIG. 1, a buffer layer 32 may beformed on a substrate 30. The substrate 30 may be, for example, asapphire substrate, a silicon (Si) substrate, and/or a silicon carbide(SiC) substrate. A first material layer 34 may be formed on the bufferlayer 32. The first material layer 34 may be a compound semiconductorlayer. For example, the first material layer 34 may be an un-dopedgallium nitride (GaN) layer. The first material layer 34 may be, forexample, an aluminium gallium arsenide (AlGaAs) layer. The firstmaterial layer 34 may be formed by using, for example, an epitaxialgrowth method.

Referring to FIGS. 2 and 3, the first material layer 34 may be dopedwith impurities 36. The impurities 36 may be distributed throughout theentire first material layer 34 to form an impurity doped first materiallayer 34A. The first material layer 34 may be doped with the impurities36 by, for example, using an ion injection method. The impurities 36 mayinclude, for example, argon (Ar). The impurities 36 may include, forexample, a halogen element, an alkali metal, an alkali earth metal, agroup-VI element in the periodic table and/or a transition metal. Forexample, the halogen element may be neon (Ne), Ar and/or krypton (Kr).The alkali metal may be lithium (Li), sodium (Na) and/or potassium (K).The alkali earth metal may be beryllium (Be), magnesium (Mg) and/orcalcium (Ca). The group-VI element may be carbon (C), Si and/orgermanium (Ge). The transition metal may be manganese (Mn), iron (Fe)and/or chromium (Cr). By injecting the impurities 36, a latticestructure and/or a crystalline structure of the first material layer 34may be disrupted. A resistance of the impurity doped first materiallayer 34A may be a high and/or increased resistance.

Referring to FIG. 3, a second material layer 38 may be formed on theimpurity doped first material layer 34A. The second material layer 38may be formed by using, for example, an epitaxial growth method. Apolarizability and/or band gap of the second material layer 38 may begreater than a polarizability and/or band gap of the first materiallayer 34. When the second material layer 38 is formed, polarization maybe induced in the second material layer 38 due to a difference betweenthe polarizabilities of the first and second material layers 34A and 38and a 2DEG 40 may be induced in the first material layer 34A. A2-dimensional electron gas (2DEG) 40 may be induced adjacent to aninterface between the first material layer 34A and the second materiallayer 38. The second material layer 38 may be, for example, an AlGaNlayer and/or a GaAs layer.

The second material layer 38 may be patterned to form second materiallayer patterns 38S and 38D, which may be spaced apart from each other,as illustrated in FIG. 4. The second material layer pattern 38S(hereinafter, referred to as a source pattern) may define a sourceregion, and the second material layer pattern 38D (hereinafter, referredto as a drain pattern) may define a drain region. The second materiallayer 38 may be patterned by using, for example, an etch method (e.g.,an anisotropic etch). Because the 2DEG 40 may be induced according tothe polarization of the second material layer 38, the 2DEG 40 may existbelow the source pattern 38S and the drain pattern 38D, and may notexist (in an unbiased state of the HEMT) in other regions.

Referring to FIG. 5, a gate insulation layer 42 may be formed on theimpurity doped first material layer 34A between the source and drainpatterns 38S and 38D. The gate insulation layer 42 may be, for example,a silicon oxide layer and/or a nitride layer. The gate insulation layer42 may overlap with the source and drain patterns 38S and 38D. Referringto FIG. 6, a gate electrode 48 may be formed on the gate insulationlayer 42. A source electrode 44 and a drain electrode 46 may berespectively formed on the source pattern 38S and the drain pattern 38D.The source electrode 44 and the drain electrode 46 may be spaced apartfrom the gate electrode 48, and may be insulated from each other by thegate insulation layer 42. The gate electrode 48, the source electrode44, and the drain electrode 46 may be formed by forming a conductivelayer (not shown) covering the gate insulation layer 42, the sourcepattern 38S, and the drain pattern 38D, and patterning the conductivelayer by using, for example, photolithographic and etch processes.

The conductive layer may be a single layer or a multi-layer. Theconductive layer may be a metal layer and/or a silicide layer with lowcontact resistance to the source and drain patterns 38S and 38D. Thegate electrode 48 may be formed at the same time as the source and drainelectrodes 44 and 46, or before or after forming the source and drainelectrodes 44 and 46. A metal-oxide semiconductor field effecttransistor (MOSFET) type normally-off HEMT may be formed. A resistanceof the impurity doped first material layer 34A may be a high and/orincreased resistance due to the doped impurity. A current leaked outsidea transistor region A1 of the impurity doped first material layer 34A inthe source region (e.g., a buffer leakage current) may be reduced. Anelectric device separation characteristic between HEMTs formed on theimpurity doped first material layer 34A may be excellent and/or improveddue to the high resistance characteristic of the impurity doped firstmaterial layer 34A.

FIGS. 7-11 are cross-sectional diagrams illustrating methods ofmanufacturing HEMTs according to other example embodiments. Referring toFIG. 7, a substrate 30, a buffer layer 32 and a first material layer 34may be formed (e.g., sequentially formed). A growth blocking layer 50may be formed on the first material layer 34. The growth blocking layer50 may be a material layer blocking and/or interrupting epitaxialgrowth. The growth blocking layer 50 may not be formed on an entire topsurface of the first material layer 34. The growth blocking layer 50 maybe formed on regions excluding a source region S1 and a drain region D1,which may be spaced apart from each other, on the top surface of thefirst material layer 34.

The growth blocking layer 50 formed on the first material layer 34between the source and drain regions S1 and D1 may define a gate regionin which a gate electrode may be formed. A thickness of the growthblocking layer 50 may be thin enough for impurities 36 to pass throughduring a doping process. The growth blocking layer 50 may be anamorphous layer, for example, an oxide layer and/or a nitride layer. Theimpurities 36 may be injected into the first material layer 34, forexample, after forming the growth blocking layer 50. Because thethickness of the growth blocking layer 50 may be thin enough for theimpurities 36 to pass through, the impurities 36 may be injected intothe entire first material layer 34. FIG. 8 illustrates the impuritydoped first material layer 34A into which the impurities 36 have beeninjected. A resistance of the impurity doped first material layer 34Amay be a high resistance.

Referring to FIG. 9, a source pattern 52S and a drain pattern 52D may berespectively formed on the source and drain regions S1 and D1 of theimpurity doped first material layer 34A. The source and drain patterns52S and 52D may be formed by using, for example, an epitaxial growthmethod. Because regions excluding the source and drain regions S1 and D1on the top surface of the impurity doped first material layer 34A arecovered by the growth blocking layer 50, a material layer may not begrown on the regions excluding the source and drain regions S1 and D1while growing source and drain patterns 52S and 52D. A band gap and/orpolarizability of the source and drain patterns 52S and 52D may begreater than a band gap and/or polarizability of the impurity dopedfirst material layer 34A.

Because the source and drain patterns 52S and 52D may be respectivelyformed on the source and drain regions S1 and D1, the 2DEG 40 may beinduced in the source and drain regions S1 and D1 of the impurity dopedfirst material layer 34A and may not be induced outside of the sourceand drain regions S1 and D1. The source and drain patterns 52S and 52Dmay be formed, for example, to a same thickness as the growth blockinglayer 50. The growth blocking layer 50 may be removed (e.g., afterforming the source and drain patterns 52S and 52D). FIG. 10 mayillustrate a resultant product after the growth blocking layer 50 isremoved. As illustrated in FIG. 10, the source and drain patterns 52Sand 52D may be spaced apart from each other on the impurity doped firstmaterial layer 34A.

Referring to FIG. 11, a gate insulation layer 42 may be formed on theimpurity doped first material layer 34A between the source and drainpatterns 52S and 52D. The gate electrode 48 may be formed on the gateinsulation layer 42. A source electrode 44 may be formed on the sourcepattern 52S. A drain electrode 46 may be formed on the drain pattern52D. Relationships and forming methods of the gate insulation layer 42,the gate electrode 48, the source electrode 44, and the drain electrode46 may be identical or similar to those described with respect to FIGS.1-6. Because the thickness of the growth blocking layer 50 may be thinenough for the impurities 36 to pass through, a threshold voltage of theHEMT may be adjusted according to the injection of the impurities 36.Because the gate electrode 48 may be formed on a location where thegrowth blocking layer 50 may be removed, a normally-off HEMT may bemanufactured without having to perform a separate gate patterningprocess. A distribution of the impurities 36 may be non-uniform in thefirst material layer 34A.

FIGS. 12-17 are cross-sectional diagrams illustrating methods ofmanufacturing HEMTs according to still other example embodiments. Agrowth blocking layer 60 of example embodiments described with respectto FIGS. 12-17 may be thicker than a growth blocking layer 50 of exampleembodiments described with respect to FIGS. 7-11. For example, thicknessof a growth blocking layer 60 may be such that the impurities 36 may notpass through. Functions of a growth blocking layer 60 may be identicalor similar to those of a growth blocking layer 50. A process of formingthe growth blocking layer 60 on the first material layer 34 andinjecting the impurities 36 shown in FIG. 12 may be performed in thesame or similar manner to that described with reference to FIG. 7. Amaterial of the growth blocking layer 60 may be identical or similar tothat of the growth blocking layer 50. A thickness of the growth blockinglayer 60 may be thicker than a thickness of a growth blocking layer 50,and may be thick enough to block the impurities 36.

When impurities 36 are injected as illustrated in FIG. 12, theimpurities 36 may not be injected into a region of the first materiallayer 34 covered by the growth blocking layer 60. The impurities 36 maybe injected into source and drain regions S1 and D1 of the firstmaterial layer 34, and the first material layer 34 may include the firstand second impurity regions 34A1 and 34A2, which may be spaced apartfrom each other, as illustrated in FIG. 13. Because the impurities 36may not be injected into a region of the first material layer 34 where agate electrode may be formed due to the growth blocking layer 60, athreshold voltage Vth of the HEMT may not be increased and/orexcessively increased.

Referring to FIG. 14, the source pattern 52S and the drain pattern 52Dmay be respectively grown on the first and second impurity regions 34A1and 34A2 of the first material layer 34. Thicknesses of the source anddrain patterns 52S and 52D may be thinner than a thickness of the growthblocking layer 60. The growth blocking layer 60 may be removed (e.g.,after forming the source and drain patterns 52S and 52D). A mask (notshown) for masking the source and drain patterns 52S and 52D, and thefirst material layer 34 between the source and drain patterns 52S and52D may be formed. Second impurities (not shown) may be injected intothe first material layer 34. Due to the mask, a region of the firstmaterial layer 34 where the second impurities may be injected may belimited to an outer region of the source pattern 52S and an outer regionof the drain pattern 52D. Referring to FIG. 15, a third impurity region34A3 may be formed on the outer region of the source pattern 52S, and afourth impurity region 34A4 may be formed on the outer region of thedrain pattern 52D.

The second impurities may be identical or similar to the impurities 36,and thus effects of the second impurities may be identical or similar tothe impurities 36. Because the third or fourth impurity regions 34A3 or34A4, which may be high resistance regions, exist between HEMTs formedon the first material layer 34 due to the injection of the secondimpurities, the HEMTs may be electrically separated (e.g., completelyisolated) from each other. Injection energy of the second impurities maybe less than injection energy of the impurities 36. The third and fourthimpurity regions 34A3 and 34A4 may exist in an upper portion of thefirst material layer 34 as shown in FIG. 15. Depths of the third andfourth impurity regions 34A3 and 34A4 may be shallower or deeper thanillustrated in FIG. 15 according to the injection energy of the secondimpurities. The mask may be removed (e.g., after injecting the secondimpurities).

A process of forming the gate insulation layer 42, which may partiallyextend onto the source and drain patterns 52S and 52D from the firstmaterial layer 34 between the source and drain patterns 52S and 52D, anda process of forming the gate electrode 48 on the gate insulation layer42, and forming the source and drain electrodes 44 and 46 respectivelyon the source and drain patterns 52S and 52D, are illustrated in FIG.16. Such processes may be identical or similar to those described withrespect to FIGS. 1-11.

Because the gate electrode 48 may be simply formed in a location wherethe growth blocking layer 60 may be removed, a normally-off HEMT may beformed without performance of a separate gate patterning process.According to at least one example embodiment, regions corresponding tothe third and fourth impurity regions 34A3 and 34A4 may be removed fromthe first material layer 34 as illustrated in FIG. 17, by using, forexample, a mesa process. For example, instead of forming the third andfourth impurity regions 34A3 and 34A4 on the first material layer 34 asshown in FIG. 15, regions corresponding to the third and fourth impurityregions 34A3 and 34A4 may be removed from the first material layer 34.An effect of removing the regions corresponding to the third and fourthimpurity regions 34A3 and 34A4 may be identical or similar to an effectof forming the third and fourth impurity regions 34A3 and 34A4.

FIGS. 18-20 are cross-sectional diagrams illustrating methods ofmanufacturing HEMTs according to yet other example embodiments.Referring to FIG. 18, a first growth blocking layer 50A and a secondgrowth blocking layer 50B may be formed on the first material layer 34.The second growth blocking layer 50B may be thicker than the firstgrowth blocking layer 50A, or vice versa. The second growth blockinglayer 50B may define a gate region. The first growth blocking layer 50Amay define the source and drain regions S1 and D1. Materials of thefirst and second growth blocking layers 50A and 50B may be identical orsimilar, and may be identical or similar to those of the growth blockinglayers 50 and 60 according to example embodiments.

The impurities 36 may be injected into the first material layer 34(e.g., after forming the first and second growth blocking layers 50A and50B). Due to a difference between thicknesses of the first and secondgrowth blocking layers 50A and 50B, the impurities 36 may not beinjected into the first material layer 34 below the second growthblocking layer 50B as illustrated in FIG. 19. The impurities 36 may beinjected through the second growth blocking layer 50A. The firstmaterial layer 34 may include fifth and sixth impurity regions 34B1 and34B2, which are spaced apart from each other, as illustrated in FIG. 19.The source and drain patterns 52S and 52D may be respectively formed onthe source and drain regions S1 and D1 of the first material layer 34.The gate insulation layer 42, the gate electrode 48, the sourceelectrode 44, and the drain electrode 46 may be formed as shown in FIG.20, identically or similarly to example embodiments described withreference to FIGS. 1-17.

According to the one or more example embodiments a buffer leakagecurrent may be reduced by increasing the electric resistance of amaterial layer including a 2DEG. Device separation characteristicsbetween neighbouring HEMTs may be increased by using methods ofmanufacturing HEMTs according to example embodiments.

While example embodiments have been particularly shown and described, itwill be understood by one of ordinary skill in the art that variationsin form and detail may be made therein without departing from the spiritand scope of the claims.

1. A method of manufacturing a high electron mobility transistor (HEMT),comprising: forming a first layer including a first material on asubstrate; increasing an electrical resistance of at least a part of thefirst layer; forming a source pattern and a drain pattern spaced apartfrom each other on the first layer, the source and drain patternsincluding a second material, a band gap of the second material greaterthan a band gap of the first material; forming a gate insulation layeron the first layer between the source pattern and the drain pattern;forming a gate electrode on the gate insulation layer; forming a sourceelectrode on the source pattern; and forming a drain electrode on thedrain pattern.
 2. The method of claim 1, wherein the increasing of theelectrical resistance of the part of the first layer includes injectingimpurities into the first layer.
 3. The method of claim 1, wherein theforming of the source pattern and the drain pattern includes forming asecond layer including the second material on the first layer, andpatterning the second layer.
 4. The method of claim 1, wherein theforming of the source pattern and the drain pattern includes forming agrowth blocking layer on a channel region and a peripheral region of thefirst layer such that regions of the first layer corresponding to thesource and drain patterns are exposed, depositing the second materialonto the exposed regions of the first layer, and removing the growthblocking layer.
 5. The method of claim 4, wherein the increasingincludes injecting impurities into the first material, and the forming asource pattern and a drain pattern includes forming the growth blockinglayer to a thickness that substantially blocks the impurities fromreaching the first layer during the injection of the impurities.
 6. Themethod of claim 4, wherein the increasing includes injecting impuritiesinto the first layer, and the forming a source pattern and a drainpattern includes forming the growth blocking layer to a thickness thatthe impurities are penetrated during the injection of the impurities. 7.The method of claim 4, wherein the forming a source pattern and a drainpattern includes forming the growth blocking layer on the channel regionto a different thickness from the growth blocking layer on theperipheral region.
 8. The method of claim 5, further comprising:injecting impurities into the peripheral region after the removing ofthe growth blocking layer.
 9. The method of claim 2, wherein the formingof the source pattern and the drain pattern includes forming a growthblocking layer on a channel region and a peripheral region of the firstlayer such that the regions of the first layer corresponding to thesource and drain patterns are exposed, depositing the second materialonto the exposed regions of the first layer, and removing the growthblocking layer.